Substrates that include one or more layers of semiconductor material are used to form a wide variety of semiconductor structures and devices including, for example, integrated circuits (ICs) (e.g., logic processors and memory devices), radiation emitting devices (e.g., light emitting diodes (LEDs), resonant cavity light emitting diodes (RCLEDs), and vertical cavity surface emitting lasers (VCSELs)), radiation absorbing devices (e.g., optical sensors and solar cells) and switching/rectifying devices (e.g., power electronic devices). Such devices may comprise bipolar junction transistors (BJTs), power metal-oxide-field-effect-transistor (MOSFETS), thyristors, schottky diodes, junction field effect transistors (JFETs), insulated gate bipolar transistors (IGBTs) and PIN diodes. Such semiconductor devices are conventionally formed in a layer-by-layer manner (i.e., lithographically) on a semiconductor substrate.
Historically, a majority of such semiconductor substrates that have been used in the semiconductor device manufacturing industry have comprised thin discs or “wafers” of silicon material. Such wafers of silicon material are fabricated by first forming a large generally cylindrical silicon single crystal ingot, and subsequently slicing the single crystal ingot perpendicularly to its longitudinal axis to form a plurality of silicon wafers. Such silicon wafers may have diameters as large as about thirty centimeters (30 cm) or more (about twelve inches (12 in.) or more). Although silicon wafers generally have thicknesses of several hundred microns (e.g., about 700 microns) or more, only a very thin layer (e.g., less than about three hundred nanometers (300 nm)) of the semiconductor material on a major surface of the silicon wafer is actually used to form active devices on the silicon wafer.
It has been discovered that the speed and power efficiency of semiconductor devices can be improved by electrically insulating the portion of the semiconductor material that is actually used to form the semiconductor devices from the remaining bulk semiconductor material of the substrate. In addition, it has more generally been discovered that providing the semiconductor material used to form the semiconductor devices upon a base substrate, comprising one or more materials, allows for “engineering” of the properties of the semiconductor material.
As a result, so-called “engineered substrates” have been developed that may include a relatively thin layer of semiconductor material (e.g., a layer having a thickness of less than about three hundred microns (300 μm)) disposed upon one or more other material, such as, for example, dielectric material (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), silicon (Si) or aluminum oxide (Al2O3)). Optionally, the layer of dielectric material may be relatively thin (e.g., too thin to enable handling by conventional semiconductor device manufacturing equipment), and the layer or layers of material over which the semiconductor material is disposed (i.e., the base substrate) may be thick enough to enable handling of the engineered substrate by manufacturing equipment.
A wide variety of engineered substrates are known in the art and may include semiconductor materials such as, for example, silicon (Si), germanium (Ge), silicon carbide (SiC), III-V type semiconductor materials, and II-VI type semiconductor materials.
For example, an engineered substrate may include an epitaxial layer of III-V type semiconductor material on a surface of a base substrate, such as, for example aluminum oxide (Al2O3) (which is often referred to as “sapphire”). Using such an engineered substrate, additional layers of material may be formed and processed (e.g., patterned) over the epitaxial layer of III-V type semiconductor material to form one or more semiconductor devices on the engineered substrate.
When a layer of semiconductor material is epitaxially grown at elevated temperatures upon an engineered substrate, lattice strain may be induced in the crystal lattice of the layer of semiconductor material. The strain in the semiconductor material may result from a lattice parameter mismatch between the crystal lattice of the underlying materials of the engineered substrate and that of the semiconductor material being formed thereon (e.g., the underlying material has one or more lattice constants that differ from that of the semiconductor material).
In addition, a lattice strain may also be induced in the crystal lattice of the semiconductor material during epitaxial growth at elevated temperature due to a difference in the coefficients of thermal expansion (CTE) exhibited by the respective adjacent materials. For example, if the underlying engineered substrate has a mean CTE which is greater than that of the semiconductor material being grown upon the engineered substrate, the semiconductor material may be grown in a state of tensile strain. Such a state of tensile strain may increase during the growth of the semiconductor material as the layer thickness increases, and may eventually result in the formation of defects in the semiconductor layer. Such defects may include, for example, dislocations and cracks.